1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, more particularly to a semiconductor device comprising an MIM (Metal-Insulator-Metal) capacitance element and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, as a capacitance element is often adopted an MIM capacitance element having a parasitic resistance and a parasitic capacitance significantly smaller than those of a conventional MOS capacitance element. In a high-frequency analog integrated circuit used in the field of mobile communication or the like, in particular, it is demanded that a more effective MIM capacitance element in which the parasitic resistance and the parasitic capacitance are further reduced be developed in order to improve an operation speed and reduce power consumption. In view of the reduction of the parasitic resistance and the parasitic capacitance in wiring, Cu multilayered wiring (Cu interconnect), which is generally used in a system LSI, is adopted increasingly often in the high-frequency analog integrated circuit.
FIGS. 5 and 6 are sectional views illustrating structures of conventional MIM capacitance elements formed in the Cu multilayered wiring, which are recited in 2006-310894 of the Unexamined Japanese Patent Applications Laid-Open. In the MIM capacitance element illustrated in FIG. 5, an insulation film 102, which is an insulating isolation film, is formed on a semiconductor substrate 101, and a first interlayer insulation film 103 is formed on the insulation film 102. In the first interlayer insulation film 103, a first wiring layer 106 (comprising a first Cu layer 105 and a first barrier metal film 104) is formed. A first barrier insulation film 107 (made of SiN film) is formed on the first interlayer insulation film 103 and the first wring layer 106 for the purpose of the diffusion of Cu and the prevention of oxidation. An MIM capacitance element 111 is formed on the barrier insulation film 107. The MIM capacitance element 111 comprises a capacitance lower electrode 108a which is made of a first TiN film 108, a capacitance insulation film 109a which is made of a second SiN film 109, and a capacitance upper electrode 110a which is made of a second TiN film 110. A second interlayer insulation film 112 is formed on the barrier insulation film 107 and the MIM capacitance element 111. In the second interlayer insulation film 112 are formed a wiring plug 115a (connected to the first wiring layer 106), a second wiring layer 115c (the wiring plug 115a and the second wiring layer 115c both comprise a second Cu layer 114 and a second barrier metal film 113), a capacitance lower electrode plug 115b (connected to the capacitance lower electrode 108a), capacitance lower electrode wiring 115d (the capacitance lower electrode plug 115b and the capacitance lower electrode wiring 115d both comprise the second Cu layer 114 and the second barrier metal film 113), and a capacitance upper electrode connecting section 115e (comprising the second Cu layer 114 and the second barrier metal film 113, and connected to the capacitance upper electrode 110a). A second barrier insulation film 116 (SiN film) is formed on the second interlayer insulation film 112, second wiring layer 115c, capacitance lower electrode wiring 115d, and capacitance upper electrode wiring 115e. 
FIG. 6 is a sectional view illustrating a constitution of an MIM capacitance element having a structure different to that of the MIM capacitance element illustrated in FIG. 5. In the MIM capacitance element, a Cu layer and a barrier metal layer constitute a capacitance lower electrode. In FIG. 6, an insulation film 202, which is an insulating isolation layer, is formed on a semiconductor substrate 201, and a first interlayer insulation film 203 is formed on the insulation film 202. In the first interlayer insulation film 203, a first wiring layer 206 and a capacitance lower electrode 207a are formed. A first Cu layer 205 and a first barrier metal film 204 constitute the first wiring layer 206 and the capacitance lower electrode 207a. A capacitance insulation film 208a which is made of a first SiN film 208, and a capacitance upper electrode 209a which is made of a first TiN film 209 are formed on the capacitance lower electrode 207a to constitute an MIM capacitance element 210. A second interlayer insulation film 211 is formed on the first wiring layer 206, MIM capacitance element 210, and interlayer insulation film 203. In the second interlayer insulation film 211, a wiring plug 214a (connected to the first wiring layer 206), a second wiring layer 214c, a capacitance lower electrode plug 214b (connected to the capacitance lower electrode 207a), a capacitance lower electrode wiring 214d, and a capacitance upper electrode connecting section 214e are formed. A second Cu layer 213 and a second barrier metal film 212 constitute the wiring plug 214a, second wiring layer 214c, and capacitance lower electrode plug 214b. The second Cu layer 213 and the second barrier metal film 212 constitute the capacitance upper electrode connecting section 214e. The capacitance upper electrode connecting section 214e is connected to a capacitance upper electrode 209a. A second barrier insulation film 215 (SiN film) is formed on the second interlayer insulation film 211, second wiring layer 214c, capacitance lower electrode wiring 214d, and capacitance upper electrode connecting section 214e. 
However, in the MIM capacitance element illustrated in FIG. 5, it is necessary to reduce the thickness of the capacitance lower electrode film 108a (first TiN film 108) to approximately 40 nm in order to form a wiring connection hole and a capacitance lower electrode connection hole at the same time, and a sheet resistance of the capacitance lower electrode 108a is thereby approximately 50Ω/□. In the MIM capacitance element conventionally used in a high-frequency analog integrated circuit having the aluminum multilayered wiring structure, an AlCu film having the thickness of approximately 500 nm generally constitutes the capacitance lower electrode, wherein the sheet resistance of the capacitance lower electrode was approximately 70 mΩ/□. Therefore, in the MIM capacitance element illustrated in FIG. 5, the parasitic resistance is significantly larger than the parasitic resistance generated in the MIM capacitance element conventionally used in the high-frequency analog integrated circuit. As a result, it becomes impossible to obtain targeted high-frequency characteristics.
Further, as illustrated in a planar structure of an MIM capacitance element in FIG. 7A, a pull-out portion 115f is conventionally provided in the capacitance upper electrode connecting section 115e of the MIM capacitance element illustrated in FIG. 5, though it is not recited in the foregoing document. The capacitance upper electrode connecting section 115e is pulled out of the region of the capacitance lower electrode 108a via the pull-out portion 115f, and connected to another wiring layer in the integrated circuit. FIG. 7B is a sectional view of the MIM capacitance element including the pull-out portion 115f of the capacitance upper electrode connecting section 115e (sectional view cut along A-B line in FIG. 7A).
As illustrated in FIG. 7B, the capacitance upper electrode connecting section 115e, pull-out portion 115f, and capacitance lower electrode 108a are formed in the second interlayer insulation film 112, and an interval therebetween is limited by the thickness of the two layers which are the capacitance upper electrode 110a and the capacitance insulation film 109a (approximately 350 nm in the above-mentioned conventional example). In the MIM capacitance element conventionally used in the high-frequency analog integrated circuit having the aluminum multilayered wiring structure, the interval between the capacitance upper electrode wiring and the capacitance lower electrode is generally approximately 800 nm. As a result, a capacitance value 119 of a region 118 where the pull-out portion 115f of the capacitance upper electrode wiring and the capacitance lower electrode 108a overlap with each other is increased. The capacitance value 119 affects a capacitance value 120 of the MIM capacitance element as the parasitic capacitance.
On the other hand, in the MIM capacitance element illustrated in FIG. 6, because the Cu wiring layer having the thickness of approximately 300 nm is used to form the capacitance lower electrode 207a, the sheet resistance of the capacitance lower electrode 207a can be reduced to approximately 80 mΩ/□. However, the formation of dents, which is generally called dishing, occurs on the surface of the Cu layer because the Cu wiring layer of the capacitance lower electrode 207a is formed in such a way that Cu is embedded in a wiring groove and thereafter flattened by means of the CMP. The dishing is particularly eminent in the case where such a Cu layer having a large surface area as the electrodes in the MIM capacitance element is formed. Therefore, the sheet resistance of the capacitance lower electrode 207a largely varies, which makes the parasitic resistance vary more greatly. Further, the thickness of the second interlayer insulation film 211 is increased in a region where the surface of the Cu layer is significantly concave when the area of the capacitance lower electrode is large. The total thickness of the capacitance upper electrode connecting section 214e, capacitance upper electrode 209a and capacitance insulation film 208a is adjusted to be equal to the thickness of the second interlayer insulation film 211. Therefore, in the MIM capacitance element in which the area of the capacitance lower electrode is large, the depth of the wiring groove set for the second Cu layer 213 is inadequate for the groove to reach the surface of the capacitance upper electrode 209a, and consequently the electrical connection between the capacitance upper electrode connecting section 214e and the capacitance upper electrode 209a may fail. As a result, it becomes impossible to reliably form the MIM capacitance element.